1. Field of the Invention
This invention relates to circuits for preventing parasitic diodes in an MOS device from being undesirably forward biased.
2. Discussion of the Related Art
In a conventional NMOS transistor buffer circuit, the drain of the transistor is connected to a supply voltage, the body of the NMOS transistor is shorted to its source, and the source provides the output terminal for the buffer. If the transistor were in its off state and the output terminal were driven by an external power supply to a voltage that exceeded the NMOS transistor's drain voltage, the parasitic body/drain PN diode would become forward biased and clamp the transistor's output terminal to a voltage of one diode drop above the drain voltage. This forward biasing results in large currents flowing through the parasitic diode which may destroy the buffer circuit.
One solution to this problem is described in the U.S. Pat. No. 4,847,522 to Fuller et al. entitled "CMOS Amplifier/Driver Stage with Output Disable Feature."The pertinent Fuller et al. circuit and layout are shown in FIGS. 1A and 1B. Fuller et al. describe a protection circuit for NMOS transistor 10 to prevent its parasitic diodes from becoming forward biased. According to Fuller et al., the P-well substrate or body 16 (FIG. 1B) for transistors 10, 12 and 14 is switched to the most negative terminal of transistor 10 by transistors 12 and 14.
During operation of the Fuller et al. circuit, when the drain of transistor 10 is more positive than its source, transistor 14 is turned on, and P-well body 16 is connected to the source of transistor 10. When the drain of transistor 10 is more negative than its source, transistor 14 is turned off and transistor 12 is turned on thus connecting the P-well body 16 to the drain of transistor 10. Thus the P-well body 16 of transistor 10 is always at the most negative voltage in an attempt to prevent any forward biasing of either source or drain junctions.
Applicants have discovered some nonobvious drawbacks of the Fuller et al. circuit described above. Applicants have discovered that the Fuller et al. circuit can be used only in cases where the voltage at the source of transistor 10 is limited to approximately the sum of the sustaining breakdown voltage of transistor 14 (about 7 volts) and the voltage at the drain of transistor 10. If this maximum voltage limit is exceeded, transistors 10 and 14 fail due to excessive current drawn by the parasitic body-source diode of transistor 10 and body-drain diode of transistor 14. A similar failure may occur via transistor 12.
Applicants have found another problem with the Fuller et al. circuit. When transistor 10 is on, both transistors 12 and 14 could be off simultaneously whenever the voltages at the drain and source of transistor 10 are very nearly the same. In such cases, the P-well body 16 just floats, and current leaks through the parasitic bipolar N-P-N transistor formed of the source, body, and drain of transistor 10.
Thus there is need for a simple and effective structure which prevents the forward biasing of diodes in an FET and which does not suffer from the above-described drawbacks of the prior art.